电子工程专辑

Design Compiler: 加速IC设计收敛的新成员

缩短设计时间和提升设计性能是目前提升半导体公司市场竞争力的关键之一。在这里请大家进一步了解一下EDA厂商的动作，以半导体设计、验证和制造的软件及知识产权供应商Synopsys公司推出的Design Compiler为例。 缩短设计时间和提升设计性能是目前提升半导体 ...
Design-Reuse

Defacto's SoC Compiler 10.0 is Released

Grenoble, France, March 9, 2023 -- Defacto Technologies just announced SoC Compiler 10.0, the new Major Release of its Front-end design solution for large SoCs. This SoC Compiler 10.0 Major Release is ...
EDN

Design Compiler 2010 Doubles Productivity of Synthesis and Place and Route

MOUNTAIN VIEW, Calif., March 29 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
Design-Reuse

Arithmatica Develops Integrated Flow with Cadence Encounter RTL Compiler to Accelerate ...

MENLO PARK, Calif. - (Business Wire) - Feb 3, 2005 - Arithmatica, Inc., the silicon math company, today announced an integrated, front-end flow for mutual customers of Arithmatica and Cadence Design ...
Electronic Design

Cadence Shoots For The Silicon Compiler Dream

It’s a long-held dream in the EDA industry: Into one end of the magic tool goes a high-level design representation of some kind, be it a functional specification a “golden” reference, or a collection ...
Electronic Design

Designing a Modern Hardware Emulation Platform

Unlike other electronic-design-automation (EDA) point tools, developing a hardware emulation for functional verification requires mastering multiple disciplines. Depending on the architecture of the ...